巴西专利BR102014011275B1 multilevel power converter, and power conversion system

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MULTILEVEL POWER CONVERTER, E, DR POWER CONVERSION SYSTEM Stages (100) and nested clamped neutral point (NNPC) multilevel power converter systems (NNPC) are presented, in which the converter stage includes an inverter core circuit NPC (110) with a floating (switched) capacitor nesting circuit (104), with the NPC core switches (110) and the switched capacitor circuit (104) being tripped using selected redundant switching states to control the voltage of the switching capacitors or achieving a multilevel output voltage having evenly spaced voltage step values. Multiple inverter stages (100) can be cascaded or connected in various configurations to implement single-phase or multi-phase power conversion systems, and higher output voltages can be achieved by forming two converter stages (100) in a configuration of bridge H, and connect multiple stages of bridge H in series with each other.
公开号:BR102014011275B1
申请号:R102014011275-8
申请日:2014-05-09
公开日:2021-05-18
发明作者:Mehdi Nariman；Bin Wu；Zhongyuan Cheng；Navid R. Zargari
申请人:Rockwell Automation Technologies, Inc.；
IPC主号:

专利说明:

HISTORIC
[001] Power converters are used to convert incoming electrical energy from one form to another to drive a load. One form of energy conversion system is a motor drive, which can be employed for variable speed operation of an electric motor load. For applications requiring very high output voltages, so-called multilevel voltage source architectures have been developed, including floating capacitor designs, clamped neutral point (NPC) designs, as well as cascade and hybrid typologies. NPC designs include a pair of capacitors connected across a DC input providing a neutral node, with each capacitor being charged to half the value of the DC input. A series of switches is connected across the DC bus, with a pair of diodes connecting intermediate switching nodes to the neutral point, the NPC converter advantageously provides a relatively simple circuit structure, but increases the number of output levels in a converter NPC increases diode switching and conduction losses and leads to greater reverse recovery current flow. In addition, high-output NPC converters suffer from uneven loss distribution of switching devices, thus limiting the maximum rated power, output current and switching frequency for a given type of switch. Furthermore, the number of clamp diodes increases substantially as the number of output levels increases. Floating capacitor designs utilize one or more capacitors that are selectively interconnected to provide the output voltage. This type of multilevel converter, however, suffers from the need for high switching frequencies to keep the capacitors properly balanced, and the voltages on the floating capacitors must be initialized. Cascade H-bridge (CHB) topologies can be used to achieve significantly high output voltage levels and high output power ratings, while allowing the use of relatively low switching frequencies and low voltage components. However, CHB designs require a significantly higher number of components to achieve regenerative operation, and a CHB converter typically requires a phase shift transformer, leading to a higher cost. Furthermore, the CHB approach requires a large number of isolated DC sources. Therefore, there remains a need for improved multilevel power systems and converter designs capable of providing multilevel inverter output capability to drive the load at variable speeds and torques. SUMMARY
[002] Several aspects of the present disclosure are now summarized to facilitate a basic understanding of the disclosure, in that this summary is not an extensive overview of the disclosure, and is intended neither to identify certain elements of the disclosure nor to delineate the scope of the same. Rather, the main purpose of this summary is to present several concepts of revelation in simplified form before the more detailed description that follows.
[003] The present disclosure provides multilevel energy converter stages as well as energy conversion systems that employ two or more such multilevel converters connected in a variety of configurations. The multilevel power converter includes an NPC-type inverter circuit nested in a switched capacitor circuit to form a nested NPC power converter (NNPC) with a controller that operates the inverter circuit and switched capacitor circuit switches to provide a voltage. multilevel output. The controller in certain embodiments employs selective choice of redundant states to control the charging and discharging of the switched capacitors to achieve a predetermined target capacitor voltage value. In certain implementations, switching control and capacitor voltage regulation advantageously guarantee capacitor voltages less than half the value of the DC input voltage, and facilitate the provision of the converter output voltage at one of multiple distinct levels of spaced steps substantially equally, thus balancing the voltage seen by the individual switching devices.
[004] In certain embodiments, the inverter circuit includes two or more inverter switches connected in series between input nodes of the inverter circuit, with an inverter output node connecting two of the inverter switching devices. The inverter further includes a clamp circuit with first and second clamp elements, such as clamp switches or diodes, connected in series between the first and second internal nodes of the inverter switching circuit, with a third internal node joining the first and second. Clip elements. The switched capacitor circuit in certain implementations includes two or more switches individually connected between one of the inverter circuit input nodes and a corresponding DC input, as well as first and second capacitors, individually connected between the corresponding inverter circuit input node and the third internal node, the controller provides switching control signals to the inverter switches and the switched capacitor circuit switching devices to provide multilevel output at the inverter output node and to control the loading and unloading of the first and second capacitors. Several implementations are possible, such as four or more distinct line-to-neutral output voltage levels. Certain implementations provide switching capacitor circuits in cascade, including multiple sets of two floating capacitors and associated switching devices for larger numbers of possible output levels.
[005] According to further aspects of the disclosure, energy conversion systems are provided, which include two or more stages or NPC converter modules. In certain embodiments, the DC inputs of two NNPC modules are connected together, with the inverter output of the first converter stage connected to a neutral node of the system, and the inverter output of the second stage providing an AC output to the system. In this way, an H NNPC bridged configuration can be achieved, and two or more such configurations can be cascaded or in series to achieve a variety of output power levels and output voltages. In addition, power conversion systems can be built using multiple sets of such modules or groups thereof to provide the multiphase outputs to drive a load. In these multistage systems, moreover, switching control can be provided to select among several redundant general switching states to achieve control over the charge and discharge of individual switched capacitors, and can facilitate the balancing of voltages seen by switching devices and advantageously provide output voltages at any suitable number of substantially evenly spaced step levels. BRIEF DESCRIPTION OF THE DRAWINGS
[006] The following description and drawings set forth certain illustrative implementations of the disclosure in detail, which are indicative of several exemplary ways in which the various principles of the disclosure may be carried out. The illustrated examples, however, are not exhaustive of the many possible realizations of the revelation. Other objects, advantages and innovative features of the revelation will be established in the following detailed description when considered in conjunction with the drawings, in which:
[007] Figure 1 is a schematic diagram illustrating a neutral point clamped multilevel power converter (NNPC) including an inverter circuit and a switched capacitor circuit with a controller using redundant switch state selection to control the load and the discharging the first and second floating capacitors to provide multilevel output voltage and to regulate the floating capacitors to one third of the DC input voltage level in accordance with one or more aspects of the present disclosure;
[008] Figure 2 is a partial schematic diagram illustrating an exemplary set of switching states for the NNPC power converter of Figure 1 to provide a four-level voltage output with substantially equally spaced steps;
[009] Figure 3 is a schematic diagram illustrating three NNPC power converters and associated DC sources to provide a three-phase voltage output to drive a motor load;
[010] Figure 4 is a graph showing a four-level line-to-neutral voltage output waveform for the NNPC power converter of Figures 1 and 2;
[011] Figure 5 is a graph illustrating a seven-level line-to-line voltage output waveform for the three-phase motor drive implementation of Figure 3;
[012] Figure 6 is a graph illustrating an exemplary level-shifted pulse width modulation implementation in the NNPC power converter controller of Figures 1 and 2;
[013] Figure 7 is a graph illustrating an exemplary space vector modulation technique for providing pulse width modulated switching control signals in the NNPC power converter controller of Figures 1 and 2;
[014] Figure 8 is a flowchart illustrating an exemplary pulse width modulation process in the NNPC power controller of Figures 1 and 2 to provide switching control signals to one or more NNPC power converters to provide an output voltage multilevel at the inverter output node and to control the charging and discharging of floating capacitors at a predetermined level;
[015] Figure 9 is a schematic diagram illustrating an NNPC H-bridge power conversion system (NNPCHB) including two-stage NNPC power converter with a first-stage inverter output providing a system neutral and inverter output the second stage providing a line voltage output to drive a motor load;
[016] Figures 10A to 10D illustrate a switching state table for providing switching control signals to the NNPC H bridge power conversion system of Figure 9 to generate a multilevel output voltage and to control charging and discharging the floating capacitors of each NNPC power converter stage;
[017] Figure 11 is a graph illustrating an exemplary seven-level line-to-neutral voltage output waveform for the NNPC H-bridge power conversion system of Figure 9;
[018] Figure 12 is a graph illustrating an exemplary 13-level line-to-line voltage output waveform for the NNPC H-bridge power conversion system of Figure 9;
[019] Figure 13 is a schematic diagram illustrating an exemplary three-phase power conversion system with three NNPC power converters configured to provide three-phase rectification to generate a DC bus voltage, and three NNPC power converters providing a three-phase AC output , with a DC bus midpoint node connected via optional impedance links to optional input and output filters;
[020] Figure 14 is a schematic diagram illustrating another exemplary three-phase power conversion system with three NNPC converters providing rectification and three NNPC converters providing an AC output, with an input transformer and a DC bus midpoint node connected through an optional impedance connection to an output filter;
[021] Figure 15 is a schematic diagram illustrating a multiphase power conversion system using three input rectifiers connected in series providing a DC bus to power NNPC converters for three output phases;
[022] Figure 16 is a schematic diagram illustrating another exemplary three-phase power conversion system with NNPC H bridge converter stages (NNPCHB) for each of the three output phases, individually driven by a multi-pulse rectifier;
[023] Figure 17 is a schematic diagram illustrating another three-phase power conversion system with multiple NNPC H bridge power converters (NNPCHB) in cascade for each phase;
[024] Figure 18 is a schematic diagram illustrating another embodiment of an NNPC power converter stage having an integral capacitor having an integral capacitor connected between the DC input terminals;
[025] Figure 19 is a schematic diagram illustrating two stages of the NNPC power converter of Figure 18 connected in series with an inductor to form a modular output phase;
[026] Figure 20 is a schematic diagram illustrating an integer number of NNPC power converter stages of Figure 18 connected in series with an inductor to form a modular output phase;
[027] Figure 21 is a graph illustrating a seven-level line-to-neutral voltage output waveform for the NNPC power converter stages of Figure 19;
[028] Figure 22 is a graph illustrating a 13-level line-to-line voltage output waveform for the NNPC power converter stages of Figure 19;
[029] Figure 23 is a schematic diagram illustrating a single phase of a cascaded NNPC-based power conversion system with an inverter output of a first NNPC converter connected to a second DC source midpoint node NNPC converter;
[030] Figure 24 is a graph showing an exemplary seven-level line-to-neutral voltage output waveform for the cascaded NNPC-based power conversion system of Figure 23;
[031] Figure 25 is a graph illustrating an exemplary 13-level line-to-line voltage output waveform for the power conversion system of Figure 23;
[032] Figure 26 is a partial schematic diagram illustrating another exemplary NNPC power converter and associated switching table in which the controller regulates the switched capacitor voltage at one quarter of the DC input voltage;
[033] Figure 27 is a partial schematic diagram illustrating another exemplary NNPC power converter and associated switching table in which the controller regulates the switched capacitor voltage at one fifth of the DC input voltage;
[034] Figure 28 is a schematic diagram illustrating another alternative NNPC power converter with multiple switched capacitor nesting stages according to additional aspects of the present disclosure; and
[035] Figure 29 is a schematic diagram illustrating another multiphase power conversion system using three input rectifiers connected in series providing a DC bus to power NNPC converters for three output phases, with auxiliary windings of the main power transformer or a separate transformer to pre-charge and balance the voltage of the switched capacitors. DETAILED DESCRIPTION
[036] Referring now to the figures, various embodiments or implementations are described below in conjunction with the drawings in which similar reference numerals are used to refer to similar elements throughout the document, and in which the various features are not necessarily drawn to scale. Power converter stages 100 are illustrated and described below, as well as power conversion systems formed by various interconnects of the illustrated converter stages 100, wherein the described nested NPC power converters (NNPC) 100 can be used to form sources of multiphase power supplies to drive any type of load, and the energy converters and energy conversion systems described can be employed in motor drives, although several concepts of the present disclosure are not limited to any specific application.
[037] Figure 1 illustrates an exemplary multilevel power converter 100, with first and second DC inputs 101 and 102, respectively, and an AC output 120 providing a single-phase AC output voltage and associated output current IOUT to drive a load ( not shown). The illustrated power converter 100 is referred to in this document as a nested clamped neutral point power converter (NNPC), and includes a switched capacitor circuit (e.g., floating capacitor) 104 nesting an NPC 110 type inverter circuit. is referred to in this document as an NNPC power converter, the central node 119 of the 110 type NPC inverter circuit does not need to be Connected to any "neutral" of the system. Power converter 100 is provided with DC electrical power input from a DC source 90 through terminals 101 and 102, where Figure 1 illustrates an exemplary input configuration including two series-connected batteries, each having a voltage value of VDC/2 with the power converter 100 thus being provided with a DC input voltage having a VDC value. In addition, while not a strict requirement of all power converter 100 implementations, the configuration shown in Figure 1 includes a neutral node "N" connected to the connection point of the two batteries of the DC input source 90. Any source Suitable DC 90 may be used in connection with the power converter 100, including, without limitation, one or more batteries, active and/or passive rectifiers, etc. In addition, the DC source 90 can include DC bus capacitances, either a single capacitor or any combination of multiple capacitors connected in any series and/or parallel configuration. In addition, as shown below in connection with Figure 18, certain embodiments of the NNPC 100 converter stage may include an on-board capacitance connected between DC input terminals 101 and 102.
[038] As illustrated in Figure 1, the inverter circuit 110 includes switching devices S2-S5 connected in series with each other between first and second inverter circuit input nodes 111 and 112, as well as an inverter output node 116 connecting two of the inverter switching devices S3 and S4, where the inverter output node 116 is connected directly or indirectly to the AC output terminal 120 of the converter 100. The inverter circuit 110, furthermore, can include any integer number of switching devices S connected in series with each other between nodes 111 and 112. In the illustrated example, four devices S2-S5 are provided, with the output node 116 having two switching devices S2 and S3 between the output 116 and the node of upper input 111, and two switches S4 and S5 connected between the output node 116 and the second input node of the inverter 112. In addition, the switched capacitor circuit 104 includes additional switches SI and S6 connected as shown between the switches. inverter switches 111 and 112 and the corresponding DC input terminals 101 and 102. Any suitable type of switching devices S1-S6 can be used on circuits 104 and 110 of power stage 100, including, without limitation, semiconductor based switches , such as isolated-gate bipolar transistors (IGBTs), silicon-controlled rectifiers (SCRs), gate-off thyristors (GTOs), integrated gate-switched thyristors (IGCTs), etc. Also, as illustrated in Figure 1, the individual switches S1-S6 include diodes to conduct current in reverse directions when the switch is off.
[039] The inverter circuit 110 of the NNPC 100 converter also includes a clamp circuit including first and second clamp elements, such as diodes D1 and D2 connected in series with each other, with the cathode D1 connected to a first internal node 114, and the anode of D2 connected to a second internal node 118. The cathode of D2 is joined to the anode of D1 at a third internal node 119. In this configuration, D1 provides a conductive path from the third internal node 119 to the first internal node 114, and D2 provides a conductive path from the second internal node 118 to the third internal node 119. Active clamp switches or other clamp elements may be used in other embodiments in place of clamp diodes as shown in the drawings. Other configurations are possible in which diodes or other clamp elements are connected in series with each other between the first and second internal nodes of the inverter switching circuit. In addition, single diodes D1 and D2 can be used as shown, or multiple diodes or other clamp elements can be used. For example, D1 may be replaced by two or more diodes in any suitable series and/or parallel configuration between nodes 119 and 114, and D2 may be replaced by two or more diodes interconnected in any suitable manner between nodes 118 and 119 Furthermore, the diodes D1 and D2 and/or the clamp diodes between the switching devices S1-S6 of the NNPC 100 converters may alternatively be clamping switches (not shown). Clamp diodes D1 and D2 can also be replaced with active switches to achieve active neutral clamping.
[040] Switched capacitor circuit 104 includes switches SI and S6 connected between possible DC input terminals 101 and 102 and one of the corresponding inverter circuit input nodes 111 and 112. In addition, switched capacitor circuit 104 includes first and second capacitors Cl and C2 individually connected between the third internal node 119 and the corresponding inverter circuit input nodes 111 and 112 as shown. Any suitable type and configuration of capacitors Cl and C2 can be used, where individual capacitors Cl and C2 can be a single capacitor or multiple capacitors connected in any suitable series and/or parallel configuration to provide a first capacitance Cl between nodes 111 and 119, as well as a second capacitance C2 between nodes 119 and 112. Furthermore, Cl and C2 are preferably or substantially equal capacitance values, although this is not a strict requirement of the present disclosure.
[041] Also referring to Figures 2 to 5, a controller 122 provides switching control signals 124-2, 124-3, 124-4 and 124-5 to the respective S2-S5 inverter switching devices and provides switching signals. switching control 124-1 and 124-6 to the switched capacitor circuit switching devices SI and S6. If the D1 and D2 clamp devices are active devices, the controller 122 also provides switching control signals to the D1 and D2 active clamp devices. Controller 122 also accepts feedback signals, such as voltages and/or currents that are not shown in the figures. Controller 122 may be implemented as part of converter 100 and/or may be a separate component or system, and a single controller 122 may provide signals 124 to multiple stages of converter 100. Converter controller 122 may be implemented using any suitable hardware , processor-executed software or firmware, or combinations thereof, wherein an exemplary embodiment of controller 122 includes one or more processing elements, such as microprocessors, microcontrollers, FPGAs, DSPs, programmable logic, etc., with "electronic memory, program memory and signal conditioning drive circuits, with the processing element(s) programmed or otherwise configured to generate the inverter switching control signals 124 suitable for operating the switching devices of the power stages 100, as well as performing other operational tasks of motor drive to drive a load. Computer-readable instructions are provided with other computer executable instructions for implementing the described power converter switching control processes and techniques, which may be stored as program instructions in an electronic memory forming a part of, or operatively associated with, another way to controller 122 .
[042] As best seen in Figure 2, control signals 124 are provided to switches S1-S6 in pulse-width modulated form in order to provide a multilevel output voltage (eg, line-to-neutral VAN voltage) at the inverter output node 116. In the illustrated embodiment, for example, controller 122 provides switching control signals 124 to switches S1-S6 so as to provide output voltage VAN at one of four line-to-voltage levels. distinct neutral. A graph 210 in Figure 4 illustrates an exemplary four-level line-to-neutral (VAN) voltage waveform 212 at inverter output node 116 relative to neutral node "N". As seen in Figure 3, in addition, three different NNPC converter stages 100 can be connected to corresponding DC sources 90 to provide AC output voltages to the phase lines of motor 202 to drive a three-phase motor load 200, with controller 122 providing a set of switching control signals 124 to each of the stages of NNPC 100. Figure 5 illustrates a graph 220 showing an exemplary line-to-line voltage waveform 222 in the system of Figure 3, in which the Controlled switching of the three NNPC 100 stages at 120° relative phase angles provides a seven-level line-to-line voltage waveform 222.
[043] Furthermore, the provision of switching control signals 124 in certain embodiments operates to control the charge and discharge of switched capacitors Cl and C2 to regulate the corresponding capacitor voltages VCi and VC2 to a target fraction of the input voltage DC VDC received at the first and second DC inputs 101, 102. The control of capacitor voltages VCi and VC2 < furthermore substantially facilitates the even distribution of voltages seen in the individual switching devices S1-S6, thus providing significant advantages. Figure 2 illustrates an exemplary switching state table 126 showing six possible switching vectors VI, V2, V3, V4, V5, and V6 corresponding to different switching states of the NNPC switching devices S1-S6, with "voltage values of corresponding line-to-neutral relative to the VDC input DC level, where "1" indicates that the corresponding switch S is 'on' or conductive. In operation, the first vector VI provides an output voltage level of +VDC/2 , the second and third switching vectors V2 and V3 are redundant with respect to the line-to-neutral output voltage, each producing a value of +VDC/6.The vectors V4 and V5 are also a pair of redundant switching state, each providing an output value of -VDC/6, and the final switching state or vector V6 produces an output voltage of -VDe/2 As seen in Figure 2, in addition, the load and the discharge of capacitors Cl and C2 are controlled through redundant vector selection, where the effect at the corresponding capacitor voltages can be different for the redundant switching states, allowing intelligent vector selection to control capacitor charging and/or discharging. For example, if the desired output voltage level should be VDC/6, vector V2 can be selected to charge Cl if the output current I0UT is positive (>0), or to discharge Cl if the output current is negative . Alternatively, selection of redundant vector V3 discharges Cl and C2 for positive output current, and these capacitors Cl and C2 if the output current is negative. As seen in table 126 of Figure 2, furthermore, similar charging and/or discharging choices can be made by selecting among the redundant vectors V4 and V5 where the desired output voltage level is -VDC/6.
[044] Also referring to Figures 6 and 7, any suitable form of pulse-width modulation switching control signal generation technique may be used in controller 122. A graph 230 in Figure 6 illustrates a per-modulation implementation. exemplary carrier-based pulse width, in which opposite polarity modulation signals 231 and 232 are used with "level-shifted triangular carrier waveforms 233, 234, and 235 to generate the switching control signals 124 for the six switches converter S1-S6. In another possible embodiment, space vector modulation can be used as shown in graph 24 0 of Figure 7, where controller 122 determines relative drive times for three control vectors Vlf V2 and V3 surrounding the current position of a reference vector Vref as shown., where the reference vector Vref has a modulation index (M) and a corresponding phase angle θ, and rotates around the diagram of space vector modulation 240 according to a desired motor position and torque in certain motor drive implementations.
[045] Referring to Figures 2 and 8, a process 250 is illustrated in the flowchart of Figure 8 to generate pulse width modulated switching control signals 124, which can be implemented in the controller 122 of the NNPC power converter controller of the Figures 1 and 2. Process 250 is illustrated and described below in the form of a series of acts or events, although the various methods of disclosure are not limited by the illustrated order of such acts or events. In this regard, unless specifically provided below, some acts or events may occur in a different order and/or concurrently with acts or events other than those illustrated and described in this document in accordance with the disclosure. If it is further noted that not all illustrated steps may be necessary to implement a process or method in accordance with the present disclosure, and one or more such acts may be combined. Illustrated method 250 and other methods of the disclosure may be implemented in hardware, software running on a processor, or combinations thereof, such as in exemplary controller 122, and may be carried out in the form of computer executable instructions stored on a computer-readable medium. tangible and non-transient, such as in a memory operatively associated with controller 122 in one example.
[046] In operation, switching control signals 124 are provided to NNPC switches S1-S6 to generate the multilevel output voltage VMI and to control the charge and discharge of capacitors Cl and C2. The example in Figure 8 is for a three-phase system (eg Figure 3 above), in which controller 122 performs space vector modulation to generate switching control signals 124 for each of the three NNPC 100 converters associated with motor phases A, B and C In certain implementations, selection of redundant switch vectors (eg from table 126 in Figure 2) is made based on one or more feedback values referring to the output current iOUT (eg IA, IB, and Ic for the three-phase example) and the switched capacitor voltages VCi and Vc2 for each of the NNPC 100 converters. As seen in Figure 8, the illustrated process 250 shows the space vector modulation processing, in which the state of desired output (eg position and torque (e of the motor) is determined in accordance with a received modulation index "M" and phase angle 9. These are received and used at 252 to identify the location of the reference vector Vref (Figure 7). The reference vector, in turn, is used to identify the three control vectors around V3, V2 and V3 (eg: Figure 7), and space vector modulation processing is used to determine the duration intervals of corresponding "turn-on time" ti, t2 and t3 at 252 in Figure 8. At 254, the control vectors and duration interval are used to determine the redundant switching states (if any) for each motor output phase that is associated with one, some, or all of the vectors around Vlz V2 and V3. For example, state table 126 in Figure 2 indicates that vector switching states V2 and V3 are redundant with each other, as are V4 and V5. Feedback is received at 256 for output currents IA, IB, and Ic, as well as switched capacitor voltages VC1 and VC2 for each phase.
[047] At 258, in Figure 8, controller 122 evaluates a cost function "J" for the redundant switching states available for each motor phase, and selects among the redundant states that minimize the cost function for the individual phases. . In the illustrated example, the cost function refers to capacitor voltages (Vci), such as voltages VC1 and VC2 in Figure 1 above, and the function uses a desired or predetermined reference value to which these capacitor voltages should be regulated (Vcref in Figure 8). In accordance with certain aspects of the present disclosure, unlike conventional NPC power converters, the target regulated floating capacitor voltage value Vcref in certain embodiments is less than VDC/2. For example, in the example in Figure 1, capacitor voltages Vcx and VC2 are controlled or regulated through intelligent redundant vector switched selection by controller 122 to be VDC/3. In other non-limiting examples, the target value Vcref may be another value that is less than half of the DC input voltage, such as VDC/4 (Figure 26 below) or VDC/5 (Figure 27).
[048] With the switching vectors selected for each of the three phases, the trigger signal generation is performed by the controller 122 at 260 in Figure 8 to generate the three sets of switching control signals 124 for the switching devices S1 -S6 of each corresponding NNPC converter stage 100. In this way, controller 122 operates to cause the proper output voltages to be provided to the load of motor 200 (Figure 3) and also regulates the voltages between capacitors Cl and C2 of each of the NNPC 100 power stages. This careful regulation of the switched capacitor voltages VCi and Vc2, in turn, facilitates the operation of the NNPC 100 converters to provide the output voltages (eg, V^j in Figure 2) at substantially evenly spaced output levels. For example, in the example in Figure 2, the output voltages are provided at four distinct levels, spaced in steps of VDC/3. Thus, the use of a smaller regulated capacitor voltage level in the illustrated NNPC converters 100 facilitates the equal distribution of voltages seen by the S1-S6 switching devices. Consequently, all switching devices S1-S6 experience the same voltage, and none of the devices need to be oversized.
[049] Also referring to Figures 9 to 12, a power converter 300 is illustrated in Figure 9 including two NNPC stages 100A and 100B as described above in connection with Figures 1 and 2, connected in an H-bridged configuration, called in this document of an NNPC H-bridge (NNPCHB). The NNPCHB 300 converter includes DC input terminals 301 and 302 receiving DC input voltage from a source 90 as described above, with input terminals 301 and 302 being connected to the DC inputs of both NNPC stages 100A and 100B as shown. Similar to the NNPC 100 converter stage in Figure 1, the first stage 100A in Figure 9 includes switching devices SAI, SA2, SA3, SA4, SA5 and SA6, as well as clamp switches or other DAI and DA2 clamp elements and capacitors CAI and CA2 having corresponding voltages VCAI and VCA2 (eg, VDC/k, where k>2). Likewise, second stage 100B includes switches SB1, SB2, SB3, SB4, SB5 and SB6, as well as clamp elements DB1 and DB2 and capacitors CB1 and CB2 with corresponding capacitor voltages VCBi and VCB2 (for example, VDC/k, where k>2). Switching devices DAI, DA2, DB1 and DB2 are shown as diodes in the drawing, but active switches such as IGBTs and IGCTs can also be used for clamp elements.
[050] The inverter output node 116 of the converter 100A in Figure 9 is connected to a neutral node of the system 306, and the inverter output node 116 of the second multilevel power converter 100B provides an AC output 304 for the power conversion system 300. Controller 122 in this case provides the switching control signals 124A to the first NNPC 100A converter, as well as a set of switching control signals 124B to the second NNPC 100B stage. In a non-limiting embodiment, controller 122 provides switching control signals in accordance with a state table or switching vector 310 shown in Figures 10A to 10D by selecting a given vector V1-V36 to provide a line-voltage. desired para-neutral VAN in one of seven possible levels. As further seen in Figure 9, furthermore, three sets of NNPCHB 300 converters can be provided, with "corresponding DC sources 90 to provide output voltages to drive a three-phase motor load 200, with controllers 122 of the corresponding converters 300 providing signals of switching control 124 according to table 310, where the output voltages for the corresponding motor phases are shifted in a possible implementation by 120°.
[051] As seen in Figures 10A-10D, with the corresponding switched capacitors regulated to the voltages of VDC/3, the possible equally spaced output voltage levels (line-to-neutral) include VDC (vector VI), 2VDC/3 (V2-V5), VDC/3 (V6-V13 vectors), 0 volts (V14-V23 vectors), - VDC/3 (V24-V31 vectors), -2VDC/3 (V32-V35 vectors) and -VDC for the V36 vector. Also, as seen in table 310, the voltage output steps are all the same (VDC/3) - A graph 320 in Figure 11 illustrates an exemplary seven-level line-to-neutral output voltage waveform 322 for the NNPC 300 H bridge power converter in Figure 9. In addition, in the illustrated three-phase example, Figure 12 shows a graph 330 with a 13-level line-to-line voltage output waveform 332.
[052] In addition, as in the NNPC 100 realizations described above, the controller 122 in the NNPCHB 300 converters advantageously selects among redundant vectors, where possible, to regulate the switched capacitor voltages on the capacitors of the constituent NNPC stages 100A and 100B . For example, redundant vectors V2-V5 (Figure 10A) provide the ability to selectively charge or discharge component capacitors CAI, CA2, CB1 and CB2 from the NNPC 10 0A and 100B stages, based on the polarity of the output current IA for the 2VDC/3 output level, and other redundant vector groups are shown in table 310 allowing controller 122 to advantageously regulate capacitor voltages VCAI, VCA2 Z VCBI and VCB2 to a desired level. In this regard, controller 122 may employ process 250 of Figure 8 as described above in operating converter 300 in certain embodiments. In addition, space vector modulation or carrier-based pulse width modulation techniques can be employed to generate the switching control signals 124 in the NNPCHB 300 converter.
[053] Also referring to Figures 13 to 17, additional aspects of the disclosure provide multilevel power conversion systems 400, 420, 430, 440 and 450 having multiple NNPC 100 power converters and/or multiple NNPCHB 300 converters. shows a non-limiting example 400 including three NNPC 100 converters coupled to an AC input power source through an optional filter 402 (inductor L, capacitor-inductor CL, LCL, etc.) that operates to receive input AC voltages at the terminals AC input switches (eg terminal 120 in Figure 1 above), with DC terminals connected to positive and negative DC bus rails, where the first set of three NNPC 100 converters provides a three-phase active rectifier. The output of these rectifier stages provides a DC bus voltage over the Ca and Cb bus capacitances as shown. In certain implementations, an optional 402 input filter neutral point can be connected to the midpoint of the DC bus or central node that joins the Ca and Cb bus capacitors via an optional 408 impedance link. The DC bus voltage is provided. as an input to the DC input terminals (terminals 101 and 102 in Figure 1 above) of another set of three NNPC 100 stages, with the inverter outputs of these stages 100 providing AC output voltages to drive a load 406 through an optional filter 404. Also, as seen in Figure 13, the midpoint of the DC link can optionally be connected to a neutral of the 404 output filter via an optional 410 impedance connection. Figure 14 illustrates another 420 three-phase system similar to the one in Figure 13 above, with an input transformer 412 providing AC input power to the first set of NNPC 100 converters. Systems 410 and 420 of Figures 13 and 14 can be used, in an example. lo non-limiting, to provide a desired output voltage, eg 2 kV to 7.2 kV, using a successive six-stage configuration of NNPC 100 for a total of 36 switches and 12 clamp diodes that can also be switch switches active clamp, where example 420 in Figure 14 additionally provides isolation through transformer 412.
[054] Figure 15 shows another multiphase system 430 having an input transformer 432 providing three-phase secondaries to each of a set of three rectifiers 434 to provide a DC link over the Ca, Cb and Cc capacitors. The resulting DC bus voltage is provided to the DC input terminals of a three-stage NNPC 100 set whose AC outputs drive a three-phase load 406 through an optional 404 output filter. diode, SCR rectifiers, two-level IGBT/lGCT rectifiers, three-level NPC, or four-level NNPC. Transformer 432 and rectifiers 434 may also be of different pulse numbers, such as 6 pulses, 12 pulses, 24 pulses, etc., in certain embodiments.
[055] Figure 16 shows another three-phase power conversion system 440 with a phase shift input transformer 432 receiving power from an AC 20 source through a 32 primary, and providing six three-phase secondaries separated at exemplary angles of 25 ° > 15°, 5o, -5o, -15° and -25°, where each secondary drives a corresponding rectifier 434 as described above, and a set of NNPCHB 300 stages (for example, Figure 9 above) are driven individually by two of rectifiers 434 to provide AC outputs through an optional output filter 404 to drive a 406 three-phase motor load. In this example, an NNPC 440 H bridge multiphase rectifier system is thus provided using a 36-pulse 432 transformer to achieve the desired output voltage, eg 10 kV to 15 kV. In a possible alternative implementation, double 18-pulse transformers can be provided, or other combinations of phase shift angles for certain numbers of pulses are possible, or using different numbers of DC sources in series is also possible.
[056] Figure 17 shows a cascaded NNPCHB system with a multi-pulse rectifier for a desired output voltage, eg 10 kV to 15 kV, again using a 36-pulse transformer 432 as described above in connection with Figure 16. In this case, each NNPC 300 H bridge stage is powered by a corresponding rectifier 434 driven from a corresponding secondary of transformer 432, where each stage 300 includes a pair of NNPC stages connected as shown above in Figure 9. A In this regard, each output phase is driven by a pair of NNPC 300 H bridge stages, with the AC output of a first stage 300 connected to a motor phase (via an optional output filter 404), and the neutral of that stage 300 is connected to the AC output of second stage 300, with the neutral terminal of second stage 3 30 being connected to a neutral of system N. 0 number of transformer secondary windings and DC rectifiers, the displacement angles phase change between the transformer secondary windings, and other design parameters can be varied for this cascade NNPCHB topology.
[057] Also referring to Figures 18 to 22, Figure 18 shows another embodiment of NNPC 500 (NNPC') power converter stage with an integral capacitor C3 connected between the DC input terminals 101 and 102. Figure 19 illustrates an exemplary system 510 employing two such NNPC' 500 stages to provide a phase output through an output inductor 502, with a positive DC voltage being applied to the AC terminal 120 of the first stage 500, and the lower DC terminal 102 of the first stage 500 being connected to one end of inductor 502. The lower end of inductor 502 is connected to AC terminal 120 of second stage 500, which lower DC terminal 102 is connected to the lower (negative) terminal of the DC source. A central tap connection of inductor 502 provides the phase output (A), and multiple such configurations 510 can be used to energize a multiphase load (not shown). Figure 20 shows a modular multilevel system based on NNPC 520, in which an integer number of NNPC' 500 stages are connected as described above, with a first set of stages 500 being connected between the upper DC line and the upper end of the inductor 502, and a second set of stages 500 being connected between the lower inductor terminal and the lower DC line. Figure 21 provides a graph 530 showing a line-to-neutral voltage output waveform 532 for the 510 system of Figure 19 (using two stages of NNPC' 500) providing a line-to-neutral output voltage of seven levels. In addition, graph 540 in Figure 22 shows a line-to-line voltage output waveform 542 providing 13 voltage levels.
[058] Also referring to Figures 23 to 25, Figure 23 shows a single phase of another exemplary system 600 using a two-cell cascade NNPC configuration or stages of NNPC 100 and corresponding DC sources 90. Other implementations are also possible. using more than two NNPC 100 cells connected in a similar way. As seen in the example in Figure 23, a system neutral "N" is connected to a midpoint of the DC input source 90 to a first cell 100 whose AC output is connected to the midpoint of the DC source 90 to the (second) cell higher 100. The AC output of the second cell 100, in turn, provides the output voltage for the phase being driven by system 600. In this configuration, operation of controller(s) 122 provides a voltage waveform 7-level line-to-neutral output waveform 612 as shown in graph 610 of Figure 24, as well as a 13-level 1line-to-line output waveform 622 in graph 620 of Figure 25 for multiphase implementations.
[059] Figure 26 illustrates another exemplary NNPC power converter implementation 100, in which controller 122 provides switching control signals 124 in accordance with illustrated switching state table 700 to operate switches SI to S6 to provide multilevel output voltage at the inverter output node (AC) as well as controlling the charging and discharging of switched capacitor Cl and C2. In this implementation, however, operation of controller 122 regulates capacitor voltages VCi and VC2 to approximately a quarter of the DC bus voltage level (VDC/4). In addition, the phase output (VAU) illustrated in Figure 26 has equally spaced steps of VDC/4.
[060] Another possible implementation is shown in Figure 27, in which controller 122 operates in accordance with state table 800 to provide switching control signals 124 to generate a multilevel voltage output at one of six different levels spaced by approximately one-fifth the dc input voltage (VDC/5), with controller 122 operating to regulate the capacitor voltages at approximately one-fifth the dc input voltage level.
[061] Figure 28 shows another NNPC 900 power converter, in this case including multiple switched capacitor nesting stages configured around an NPC 110 core circuit. This 900 nested power converter includes a 110 inverter circuit, a switched capacitor circuit 104 and a controller 122. As in the above-described NNPC cell 100 of Figure 1, the inverter circuit 110 in converter 900 of Figure 28 includes switching devices S3-S6 connected in series with each other between the input nodes of the inverter circuit 111 and 112, with "an inverter output node 116 connecting S4 and S5 . In addition, the inverter circuit 110 includes clamp switches or other clamp elements D1 and D2 connected in series with each other between first and second internal nodes 114 and 118 around switches S4 and S5 as shown. The clamp circuit also includes a third internal node 119 joining clamp elements D1 and D2. The clamp devices in the drawing are shown as diodes. However, active keys, such as IGBTs and IGCTs, can also be used for clamping purposes. Converter 900 also includes a doubly nested switched capacitor circuit 104, in which a first switch SI connected between the first DC input 101 and a fourth internal node 106, and a second switch S2 connected between the node 106 and the first input node of inverter circuit 111. In addition, a third switch S7 is connected between the second inverter circuit input node 112 and a fifth internal node 108, and a fourth switch S8 is connected between the fifth internal node 108 and the second DC input 102 .
[062] Two levels of switched capacitors connected in series C1/C2 and C3/C4 are provided in Figure 28/ with Cl connected between nodes 111 and 119 and C2 connected between nodes 119 and 112, as well as C3 connected between nodes 106 and an internal sixth node 113, and C4 connected between nodes 113 and 108. In certain implementations, nodes 113 and 119 can be joined, although this is not necessary in all realizations. Controller 122 provides switching control signals 124 to operate inverter switches S3-S6 and capacitor switching devices SI, S2, S7 and S8 to provide a multilevel output voltage at inverter output node 116, as well as to control the charge and discharge of capacitors C1-C4, for example, using the selection of redundant switch vectors as described above.
[063] Figure 29 illustrates another 1000 multiphase power conversion system that includes a transformer 432 and three input rectifiers connected in series to generate a DC bus, with the three stages of NNPC 100 providing AC output voltage waveforms through an optional output filter 404 to drive a 3 phase load 406, similar to system 430 in Figure 15 above (controller(s) 122 not separately shown in Figure 29). In addition, system 1000 of Figure 29 includes an auxiliary transformer 432' (or an auxiliary secondary winding of main transformer 432) providing AC inputs to six additional rectifiers 434, with the resulting DC output from each of the rectifiers 434 being connected between one of capacitors Cl, C2 of the corresponding NNPC 100 stages. In operation, the auxiliary or secondary transformer 432' is selectively energized to pre-charge the switched capacitors Cl and C2 of each of the stages 100 through intervening rectifiers 434, as in the energization of the general system 1000, and thus can be de-energized once system 1000 achieves steady-state operation.
[064] The above examples are merely illustrative of several possible realizations of various aspects of the present disclosure, in which changes and/or equivalent modifications will occur to other experts in the field after reading and understanding this descriptive report and the attached drawings. In particular with regard to the various functions performed by the above-described components (assemblies, devices, systems, circuits, and the like), the terms (including a reference to a "means") used to describe such components are intended to correspond, unless to the contrary, to any component, such as hardware, software executed by the processor, or combinations thereof, that performs the specified function of the described component (i.e., which is functionally equivalent), although not structurally equivalent to the revealed structure that performs the function in the illustrated implementations of the disclosure. Furthermore, although a specific feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more features from other implementations as may be desired and advantageous for any given application or specific application. In addition, to the extent that the terms "including", "includes", "having", "has", "with", or variants thereof, are used in the detailed description and/or claims, such terms are intended to be inclusive in a similar way to the term "understanding". LIST OF COMPONENTS

权利要求:
Claims (7)
[0001]
1. MULTILEVEL POWER CONVERTER (100), characterized by comprising: an inverter circuit (110), comprising: an inverter switching circuit including: a plurality of inverter switching devices (S2-S5) connected in series with each other the first and second inverter circuit input nodes (111, 112) and an inverter output node (116) connecting two of the plurality of inverter switching devices (S3, S4), and wherein the circuit inverter switching circuit comprises: a first inverter switching device (S2) with a first terminal connected to the first inverter circuit input node (111) and a second terminal connected to the first internal node (114), a second device switching device (S3) with a first terminal connected to the first internal node (114) and a second terminal connected to the inverter output node (116), a third inverter switching device (S4) with a first terminal with connected to the inverter output node (116) and a second terminal connected to the second internal node (118), and a fourth inverter switching device (S5) with a first terminal connected to the second internal node (118) and a second terminal connected to the second inverter circuit input node (112); and a clamp circuit including first and second clamp elements (D1, D2) connected in series with each other between the first and second internal nodes (114, 118) of the inverter switching circuit and a third internal node (119) joining the first and second clamp elements (D1, D2); wherein the first clamp element (D1) includes a first terminal connected to the third inner node (119), and a second terminal connected to the first inner node (114); wherein the second clamp element (D2) includes a first terminal connected to the second inner node (118) and a second terminal connected to the third inner node (119); a switched capacitor circuit (104), comprising: switched capacitor circuit switching devices (S1, S6) individually connected between a corresponding DC input (101, 102) and a corresponding inverter circuit input node (111, 112 ), and first and second capacitors (C1, C2) individually connected between one of the corresponding inverter circuit input nodes (111, 112) and the third internal node (119); and wherein the circuit switched capacitor circuit switching devices (S1, S6) further comprises: a first circuit switched capacitor circuit switching device (S1) with a first terminal connected to a first DC input (101) and a second terminal connected to the first inverter circuit input node (111), and a second capacitor switched circuit switching device (S6) with a first terminal connected to the second inverter circuit input node (112), and a second terminal connected to a second DC input (102); wherein the first capacitor (C1) includes a first terminal connected to the first inverter circuit input node (111) and a second terminal connected to the third internal node (119); and wherein the second capacitor (C2) includes a first terminal connected to the third internal node (119) and a second terminal connected to the second inverter circuit input node (112) wherein the third internal node (119) is not connected. to no neutral system a controller (122) providing switching control signals to the plurality of inverter switching devices (S2-S5) and switching capacitor circuit switching devices (S1, S2) to provide a multilevel output voltage at the inverter output node (116) and to control the charging and discharging of the first and second capacitors (C1, C2), where the control signals form six possible switching vectors V1, V2, V3, V4, V5, V6, comprising: vector V1 corresponding to a switching state in which the first switching device of the switched capacitor circuit (S1) and the first and second switching device of the inverter (S2, S3) are connected and the second switching device that of the switched capacitor circuit (S6) and the third and fourth inverter switching device (S4, S5) are off; vector V2 corresponding to a switching state in which the first capacitor switched circuit switching device (S1) and the second and third inverter switching device (S3, S4) are on and the second capacitor circuit switching device switched (S6) and the inverter's first and fourth switching device (S2, S5) are off; vector V3 corresponding to a switching state in which the first and second switching device of the inverter (S2, S3) and the second switching device of the switched capacitor circuit (S6) are connected and the first switching device of the inverter circuit. switched capacitor (S1) and the inverter's third and fourth switching device (S4, S5) are off; vector V4 corresponding to a switching state in which the first switched capacitor circuit switching device (S1) and the third and fourth inverter switching device (S4, S5) are connected and the first and second inverter switching device (S2, S3) and the second switching device of the switched capacitor circuit (S6) are off; vector V5 corresponding to a switching state in which the second and third switching device of the inverter (S3, S4) and the second switching device of the switched capacitor circuit (S6) are connected and the first switching device of the capacitor circuit switched (S1) and the first and fourth inverter switching devices (S2, S5) are off; and vector V6 corresponding to a switching state in which the third and fourth switching device of the inverter (S4, S5) and the second switching device of the switching capacitor circuit (S6) are connected and the first switching device of the circuit of the inverter. switched capacitor (S1) and the first and second inverter switching device (S2, S3) are off; and where the switch vectors V2 and V3 are redundant with each other with respect to the line-to-neutral output voltage, and where the switch vector V3 allows the first and second capacitors (C1, C2) to be charged or simultaneously discharged, and where the switch vectors V4 and V5 are redundant with each other with respect to the line-to-neutral output voltage, and where the switch vector V4 allows the first and second capacitors (C1, C2) are loaded or unloaded simultaneously.
[0002]
2. MULTILEVEL POWER CONVERTER (100) according to claim 1, characterized in that the controller (122) provides the switching control signals to the inverter switching devices (S2-S5) and to the capacitor circuit switching devices switched (S1, S2) to provide the output voltage at one of four distinct levels.
[0003]
3. MULTILEVEL POWER CONVERTER (100), according to claim 2, characterized in that the controller (122) selects from a plurality of redundant switching states for at least one of the four distinct output voltage levels in the provision of control signals switch to control the charge and discharge of the first and second capacitors (C1, C2) to regulate the first and second voltages of the corresponding capacitors (VCI, VC2) to less than half of a DC input voltage (VDC) between the first and second DC inputs (101, 102).
[0004]
4. MULTILEVEL POWER CONVERTER (100), according to claim 2, characterized in that the controller (122) provides the switching control signals to the inverter switching devices (S2-S5) and to the capacitor circuit switching devices switched (S1, S2) to provide the output voltage at one of four distinct levels of equally spaced steps.
[0005]
5. MULTILEVEL POWER CONVERTER (100) according to any one of claims 1 to 4, characterized in that the controller (122) provides the switching control signals to the inverter switching devices (S2-S5) and to the switching devices of switched capacitor circuit (S1, S2) to provide the output voltage at one of four distinct levels of evenly spaced steps.
[0006]
6. ENERGY CONVERSION SYSTEM (300, 400, 420, 430, 440, 450, 1000), characterized in that it comprises a plurality of multilevel energy converters (100), as defined in claim 1.
[0007]
7. POWER CONVERSION SYSTEM (300) according to claim 6, characterized in that the controller (122) provides the switching control signals to the inverter switching devices (S2-S5) and to the switching circuit switching devices. switched capacitor (S1, S2) to provide the output voltage of each multilevel power converter (100) at one of at least four distinct levels.

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法律状态:
2015-06-30| B03A| Publication of a patent application or of a certificate of addition of invention [chapter 3.1 patent gazette]|

2018-11-13| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|

2020-02-18| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|

2021-03-02| B06A| Notification to applicant to reply to the report for non-patentability or inadequacy of the application [chapter 6.1 patent gazette]|

2021-04-27| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|

2021-05-18| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 09/05/2014, OBSERVADAS AS CONDICOES LEGAIS. |

优先权:

申请号 | 申请日 | 专利标题

US13/922,401|2013-06-20|

US13/922,401|US9083230B2|2013-06-20|2013-06-20|Multilevel voltage source converters and systems|

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